Selectively Weighted Multicast Scheduling Designs For Input-Queued Switches

Abstract

The objective of this work is to propose hardware-efficient schemes for multicast scheduling in input-queued switches based on the weight based arbiter (WBA), motivated by the practical implementation of a scheduler for a 64-port optical crossbar switch. We demonstrate that alternating fanout- and age-based weight calculations in subsequent time slots lead to higher clock speeds and better FPGA area utilization, with performance characteristics close to the conventional WBA. Our FPGA sizing experiments and clock speed evaluations show improvements of up to 35.25% and 47.06%, respectively, over the WBA. In addition, latency-throughput results for the proposed variations highlight the trade-offs between fairness, throughput, hardware complexity and speed.