{"title":"A Real-Time Raster Scan Display for 3-D Graphics","authors":"D. Jackel, H. Günther, B. Herwig, H. Rüsseler","doi":"10.2312/EGGH/EGGH89/213-227","DOIUrl":null,"url":null,"abstract":"This paper describes the architecture of a raster scan display for real-time visualisation of shaded polygons. A performance of 15-106 Phong shaded pixels per second is a primary goal of a pipelined rendering processor. The performance of the geometry processor, which is responsible for the geometrical transformations, the 3-d clipping and the perspective projection, will exceed 100,000 triangle shaped polygons. \n \nFollowing a survey of the entire 3-d real-time system, we will describe architectural details of the rendering processor. Finally, the main features enabled by the architecture are highlighted.","PeriodicalId":206166,"journal":{"name":"Advances in Computer Graphics Hardware","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Advances in Computer Graphics Hardware","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.2312/EGGH/EGGH89/213-227","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper describes the architecture of a raster scan display for real-time visualisation of shaded polygons. A performance of 15-106 Phong shaded pixels per second is a primary goal of a pipelined rendering processor. The performance of the geometry processor, which is responsible for the geometrical transformations, the 3-d clipping and the perspective projection, will exceed 100,000 triangle shaped polygons.
Following a survey of the entire 3-d real-time system, we will describe architectural details of the rendering processor. Finally, the main features enabled by the architecture are highlighted.