Comparison of resistor matching performance of polysilicon films in a CMOS process

Abstract

Matched pairs or arrays of resistive elements are an important aspect of many analog and mixed signal semiconductor circuit designs. Such structures are often implemented using the polysilicon layers in a typical CMOS process. In many processes, there are two or more such layers at the disposal of the designer. These typically have differing resistivity characteristics and matching performance. This paper examines the resistance matching characteristics of the polysilicon layers on a commercial CMOS process. The study encompasses both wafer-to-wafer and die-to-die variations, and presents models to describe the behavior. Using these models, conclusions are drawn regarding the appropriate layer to use to minimize the silicon area for target values of resistance and matching.