An FPGA Implementation of On-Chip Trainable Multilayer SAM Spiking Neural Network

Abstract

This paper describes an implementation of a multilayer SAM spiking neural network into the PL logic part (FPGA) in a Xilinx Zynq processor. The SAM neuron model is a type of one of the most popular LIF spiking neuron model. The SAM neural network can be an on-chip trainable model because the model does not require any multiplier under our proposed Back Propagation (BP) base training algorithm. As a result, the model achieved an XOR logic element in a unit of spikes. Moreover, we achieved a multiplier-less implementation with our intended algorithm and architecture. The design allows an arbitrary number setting for the hidden and output neurons.