Enhancing ESys.Net with a semi-formal verification layer

Abstract

As electronic systems reach tremendous complexity, new CAD tools are needed to cope with their design and verification. ESys.Net, a new design environment under development at Universite de Montreal proposes an elegant solution for modeling and simulation. This paper presents the extension of this environment with a complete verification layer based on linear temporal logic. This is a major enhancement to ESys.Net, since it allows designers to use it not only for modeling and simulation but also for verification.