Constraint based temporal partitioning model for partial reconfigurable architectures

Abstract

Partial reconfiguration has opened the door to efficient implementation of large applications on area constrained hardware. It requires a divide and mapping technique through which large applications are divided and mapped on reconfigurable hardware. A technique is proposed for dividing the application taking into account implementation and architectural constraints on hardware processing elements which are swappable. Each time a new task is mapped, an objective function considers mapping of the new task on existing PE or loading a new configuration bit stream for an optimized PE. The decision is critical because it can minimize configuration time at the cost of execution time.