A method for reducing power consumption of CMOS logic based on signal transition probability

Abstract

Some CMOS gates are topologically asymmetric in inputs, even though they are logically symmetric. It implies a possibility to reduce power consumption by optimizing signal assignment to the inputs. In this study we theoretically derive power consumption of a 2-input NAND gate based on transition probability of input signals, with taking into account charging current due to an internal node. We also propose a signal assignment method to input terminals for reducing power consumption by extending our method for large circuits, and demonstrate the effect of power consumption reduction by the present method.<>