Design of Energy Efficient True Random Number Generator using MUX-Metastable Approach

Dhirendra Kumar, Himanshu Kesarwani, Kavindra Kandpal, P. K. Misra, M. Goswami
{"title":"Design of Energy Efficient True Random Number Generator using MUX-Metastable Approach","authors":"Dhirendra Kumar, Himanshu Kesarwani, Kavindra Kandpal, P. K. Misra, M. Goswami","doi":"10.1109/SPIN52536.2021.9566149","DOIUrl":null,"url":null,"abstract":"The design of a meta-stable ring oscillator-based true random number generator (TRNG) is presented in this paper. The proposed circuit is designed in 40nm CMOS technology and simulated in cadence virtuoso simulation environment using a combination of current starved-based ring oscillators (ROs), multiplexer, linear feedback shift register (LFSR), UP/DOWN counter followed by a meta-stable circuit. The current starved inverter-based RO is used in place of the power-hungry comparator to save a significant amount of power dissipation observed in the existing design. The metastable circuit is used for providing randomness in the design. The proposed design had resulted in the generation of approximately 40Mbps speed, the power dissipation of 730μW, and energy efficiency of 18.25pJ/bit when designed at 1.1V. The design is fully validated by NIST 800.22 statistical test suite. The proposed design is thus highly suitable for random number generation.","PeriodicalId":343177,"journal":{"name":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 8th International Conference on Signal Processing and Integrated Networks (SPIN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPIN52536.2021.9566149","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

The design of a meta-stable ring oscillator-based true random number generator (TRNG) is presented in this paper. The proposed circuit is designed in 40nm CMOS technology and simulated in cadence virtuoso simulation environment using a combination of current starved-based ring oscillators (ROs), multiplexer, linear feedback shift register (LFSR), UP/DOWN counter followed by a meta-stable circuit. The current starved inverter-based RO is used in place of the power-hungry comparator to save a significant amount of power dissipation observed in the existing design. The metastable circuit is used for providing randomness in the design. The proposed design had resulted in the generation of approximately 40Mbps speed, the power dissipation of 730μW, and energy efficiency of 18.25pJ/bit when designed at 1.1V. The design is fully validated by NIST 800.22 statistical test suite. The proposed design is thus highly suitable for random number generation.
基于mux -亚稳态方法的高效真随机数发生器设计
本文设计了一种基于元稳定环振的真随机数发生器。该电路采用40nm CMOS技术设计,并在cadence virtuoso仿真环境中进行仿真,采用基于电流不足的环形振荡器(ROs)、多路复用器、线性反馈移位寄存器(LFSR)、UP/DOWN计数器和亚稳定电路的组合。基于电流饥渴的逆变器的RO被用来代替耗电比较器,以节省在现有设计中观察到的大量功耗。亚稳电路用于在设计中提供随机性。在1.1V电压下,该设计可产生约40Mbps的速度、730μW的功耗和18.25pJ/bit的能效。该设计通过NIST 800.22统计测试套件进行了充分验证。因此,所提出的设计非常适合于随机数的生成。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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