Hardware Architecture of a Decoder for Fractal Image Compression

Abstract

Fractal image compression is a comparatively new and less explored technique in the domain of image processing. The main problem is it's very high image compression time due to the huge number of ‘range’ - ‘domain’ comparisons it has to undergo. If efficiently utilised, fractal image compression gives the best compression ratio which is highest among other contemporary techniques. In this paper we have proposed efficient hardware of a decoder for the fractal image compression. Controlled parallelism has been incorporated to speed up the decoding process. The whole design has been simulated and synthesized using verilog HDL.