A 2/spl mu/m Cmos Digital Adaptive Equalizer Chip For QAM Digital Radio Modems

Abstract

The design and fabrication of a fully digital adaptive equalizer chip for QAM (quadrature amplitude modulation) digital radio modems is reported. The chip contains 107936 transistors on a silicon area of 94.6 mm/sup 2/. The chip was designed in a 2- mu m CMOS technology for a clock and sampling rate of 23.5 MHz. Accordingly, the functional throughput rate per chip area is 6.7 10/sup 11/ eq. gates Hz/cm/sup 2/. The inputs and outputs of the chip are ECL compatible, using a control unit compensating the influence of transistor parameter variations. For proper communication between chips having different technology parameters, a matched clocking scheme for synchronization was developed. A complex-valued equalizer was realized with four chips and tested in a 16-QAM digital radio modem, running at 35-MHz clock frequency. >