SOPRANO: an efficient automatic test pattern generator for stuck-open faults in CMOS combinational circuits

Abstract

The key idea of SOPRANO is to convert a CMOS circuit into an equivalent gate-level circuit and SOP faults into the equivalent stuck-at-faults. Then SOPRANO derives test patterns for SOP faults using a gate-level test pattern generator. Several techniques to reduce the test set size are introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANO achieves high SOP fault coverage and short processing time.<>