Layout-to-schematic as a step towards layout-versus-schematic verification of SFQ integrated circuit layouts

Abstract

Except for a specialized implementation in Cadence, no general automated layout-versus-schematic verification tools exist for the superconductive integrated circuit design community. This exposes superconductive circuit layouts to unintended errors. Here we present a layout-to-schematic (L2S) algorithm as the first step towards a full layout-versus-schematic verification tool for superconductive integrated circuits. We include a discussion on the L2S algorithm design, user input options to allow steering of the algorithm, and extraction results for typical circuit layouts to show that the algorithm works as intended.