A Graph-Based 3D IC Partitioning Technique

Abstract

Netlist partitioning is an important part of the physical design of 3D IC chips. Each subcircuit corresponding to a partition is subsequently assigned to a suitable device layer in the design phase. This paper proposes a netlist partitioning technique that intends to minimize the number of inter-layer interconnections while maintaining the area constraints. This, in turn, will minimize the area and cost associated with the Through-Silicon Vias (TSVs) needed in the design. The proposed method starts with an BFS-based initial solution and then improves iteratively using a heuristic. Experimental results demonstrate that by reassigning some modules to other layers, our algorithm could achieve up to 45% reduction in the number of TSVs on several benchmark circuits compared to earlier approaches. The resulting increase in floor area due to movement of modules a cross layers, is almost compensated by the decrease in TSV-area. Thus while satisfying the area-constraints, it allows us to reduce the number of TSVs as well as the IR-drop and delay associated with the vias.