60 GHz SiGe HBT downconversion mixer

V. Subramanian, Van-Hoang Do, W. Keusgen, G. Boeck
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引用次数: 14

Abstract

This work presents an active downconverter targeted for integration in 60 GHz high speed data communication RF front-ends. The designed downconverter has been realized in 0.25 mum SiGe BiCMOS technology with ft around 200 GHz. The downconverter consists of a single balanced mixer with an on-chip balun for differential to single ended conversion. High linearity and bandwidth are the main design goals rather than high gain. A clear-cut investigation of the applied bottom up design approach was presented with emphasis on modeling the critical on-chip signal path interconnects, matching and filtering components. The design and applied methodologies will be justified by comparing the measured and simulated performances. At 60 GHz an input 1-dB power compression of -5 dBm, 2.5 dB conversion gain and a gain variation around 2 dB from 50 to 70 GHz, are measured. Current consumption of the mixer core is 4.7 mA from a 3.3 V supply and the active chip area is 0.48 mm2.
本工作提出了一种针对60ghz高速数据通信射频前端集成的有源下变频器。所设计的下变频器已在0.25 μ SiGe BiCMOS技术下实现,工作频率在200 GHz左右。下变频器由一个单平衡混频器和一个片上平衡器组成,用于差分到单端转换。高线性度和高带宽是主要的设计目标,而不是高增益。对应用自底向上的设计方法进行了明确的研究,重点是对片上关键信号通路互连、匹配和滤波组件进行建模。设计和应用方法将通过比较测量和模拟性能来证明。在60 GHz时,测量了-5 dBm的输入1 dB功率压缩,2.5 dB转换增益和在50 - 70 GHz范围内约2 dB的增益变化。混频器核心的电流消耗为4.7 mA,来自3.3 V电源,有源芯片面积为0.48 mm2。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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