BBDS-a design tool for architectural evaluation and rapid prototyping of performance critical digital systems

Abstract

BBDS, an interactive graphical design tool for developing clock cycle true system models, is described. A design idea is entered through graphical interaction based on the Werner diagram. All important decisions about scheduling and allocation of operations are visually explicit. The design can rapidly be verified through simulation, timing analysis, area estimation and prototyping in programmable gate arrays. This allows very fast evaluation of an architectural idea, and allows for a series of fast iterative design improvements, BBDS also enforces a set of formally defined rules based on attributes of signals and component connectors to guarantee consistency of the clocking scheme. Both standard components and software can be accommodated. BBDS can be used to investigate the partitioning of a computer system into software and hardware, and is based on automatic synthesis with a user selectable target library.<>