An evaluation of fault-tolerant hypercube architectures for onboard computing

Abstract

Four hypercube architectures that are designed to use hardware resources more efficiently and that produce computers with high throughput and high reliability are evaluated. Spare nodes in three of the architectures are configured so that the entire computer has the topology of an incomplete hypercube. Here, the nodes of an incomplete hypercube are capable of providing different levels of fault detection, hardware reconfiguration, and routing. In the other architecture, the hypercube topology uses conventional switches capable only of establishing connections. End-of-mission dependability models and performance simulation models were developed. Results of performance degradation studies of the four architectures under reconfiguration in terms of throughput, response time, and communication utilization are presented for three workloads. The evaluations addressed performance-related dependability based on hardware failures and reconfiguration using hardware.<>