{"title":"Multiple-valued current-mode arithmetic circuits based on redundant positive-digit number representations","authors":"S. Kawahito, K. Mizuno, Tasuro Nakamura","doi":"10.1109/ISMVL.1991.130752","DOIUrl":null,"url":null,"abstract":"High-speed arithmetic algorithms and circuits based on redundant positive-digit number representations are described. To perform two-input radix-2 addition, for example, the proposed algorithm uses digit set (0, 1, 2, 3). The addition and subtraction can be performed speedily by a constant time independent of the wordlength. The n-digit multiplication and division can he performed in a time proportional to log/sub 2/ n and n, respectively. The basic arithmetic circuits are designed and implemented with multiple-valued current-mode circuits. The multiple-valued arithmetic circuits using the proposed algorithms exhibit good speed and compactness in VLSI implementation.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1991.130752","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18
Abstract
High-speed arithmetic algorithms and circuits based on redundant positive-digit number representations are described. To perform two-input radix-2 addition, for example, the proposed algorithm uses digit set (0, 1, 2, 3). The addition and subtraction can be performed speedily by a constant time independent of the wordlength. The n-digit multiplication and division can he performed in a time proportional to log/sub 2/ n and n, respectively. The basic arithmetic circuits are designed and implemented with multiple-valued current-mode circuits. The multiple-valued arithmetic circuits using the proposed algorithms exhibit good speed and compactness in VLSI implementation.<>