Multiple-valued current-mode arithmetic circuits based on redundant positive-digit number representations

S. Kawahito, K. Mizuno, Tasuro Nakamura
{"title":"Multiple-valued current-mode arithmetic circuits based on redundant positive-digit number representations","authors":"S. Kawahito, K. Mizuno, Tasuro Nakamura","doi":"10.1109/ISMVL.1991.130752","DOIUrl":null,"url":null,"abstract":"High-speed arithmetic algorithms and circuits based on redundant positive-digit number representations are described. To perform two-input radix-2 addition, for example, the proposed algorithm uses digit set (0, 1, 2, 3). The addition and subtraction can be performed speedily by a constant time independent of the wordlength. The n-digit multiplication and division can he performed in a time proportional to log/sub 2/ n and n, respectively. The basic arithmetic circuits are designed and implemented with multiple-valued current-mode circuits. The multiple-valued arithmetic circuits using the proposed algorithms exhibit good speed and compactness in VLSI implementation.<<ETX>>","PeriodicalId":127974,"journal":{"name":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991] Proceedings of the Twenty-First International Symposium on Multiple-Valued Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1991.130752","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18

Abstract

High-speed arithmetic algorithms and circuits based on redundant positive-digit number representations are described. To perform two-input radix-2 addition, for example, the proposed algorithm uses digit set (0, 1, 2, 3). The addition and subtraction can be performed speedily by a constant time independent of the wordlength. The n-digit multiplication and division can he performed in a time proportional to log/sub 2/ n and n, respectively. The basic arithmetic circuits are designed and implemented with multiple-valued current-mode circuits. The multiple-valued arithmetic circuits using the proposed algorithms exhibit good speed and compactness in VLSI implementation.<>
基于冗余正数表示的多值电流模式算术电路
描述了基于冗余正数表示的高速算法和电路。例如,为了执行双输入的基数-2加法,该算法使用数字集(0,1,2,3)。加法和减法可以通过与字长无关的常数时间快速执行。n位数的乘法和除法可以分别在与log/sub 2/ n和n成比例的时间内完成。用多值电流型电路设计并实现了基本的算法电路。采用所提出算法的多值算术电路在VLSI实现中具有良好的速度和紧凑性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信