N. Kumar, R. Swami, H. Nimishakavi, I. Nobugaki, A. Sen
{"title":"Superintegrated smart access controller","authors":"N. Kumar, R. Swami, H. Nimishakavi, I. Nobugaki, A. Sen","doi":"10.1109/ASIC.1990.186099","DOIUrl":null,"url":null,"abstract":"The smart access controller (SAC) integrated circuit is discussed. This chip has been designed to serve serial communication control applications such as terminals, printers, modems, and slave communication processes, for 8, 16- and 32-bit MPU-based systems. Enhancements and cost reductions of existing hardware using Z80/Z180 with Z8530/Z85C30 serial communication controller (SCC) applications are discussed. The SAC combines the Z80180 MPU, with a single channel, 4 channels of counter timer and two 8-bit general-purpose parallel I/O ports and includes features like low electromagnetic interference (EMI) and programmable interrupt priority daisy chain. The chip is implemented using megacell-based superintegration design methodology in 1.2 micron CMOS technology. The chip has 80000 transistors with a die size of 330*205 mils and is packaged in a 100-pin QFP package.<<ETX>>","PeriodicalId":126693,"journal":{"name":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Third Annual IEEE Proceedings on ASIC Seminar and Exhibit","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1990.186099","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The smart access controller (SAC) integrated circuit is discussed. This chip has been designed to serve serial communication control applications such as terminals, printers, modems, and slave communication processes, for 8, 16- and 32-bit MPU-based systems. Enhancements and cost reductions of existing hardware using Z80/Z180 with Z8530/Z85C30 serial communication controller (SCC) applications are discussed. The SAC combines the Z80180 MPU, with a single channel, 4 channels of counter timer and two 8-bit general-purpose parallel I/O ports and includes features like low electromagnetic interference (EMI) and programmable interrupt priority daisy chain. The chip is implemented using megacell-based superintegration design methodology in 1.2 micron CMOS technology. The chip has 80000 transistors with a die size of 330*205 mils and is packaged in a 100-pin QFP package.<>