A demonstration of build-in test design verification for a typical avionic power circuit using Matlab Stateflow

Abstract

Build in test (BIT) design is an essential way of improving testability and availability in avionic systems. Matlab based Simulink-Stateflow is an effective tool of conducting BIT design verification at airplane designing stage. In this paper, a detailed BIT Stateflow modeling procedure for a typical avionic power circuit is given with an elaborate description of circuit and Stateflow model functional structure. A brief engineering BIT Stateflow modeling method is summarized at the beginning. A novel method of modeling four types of common interference is particularly depicted followed by technical details of fault and interference modes injection, BIT logics and BIT estimation. The result indicates that the system has very considerable fault detection and isolation capability.