Fault injection into verilog models for dependability evaluation of digital systems

Abstract

This paper presents transient and permanent fault injection into Verilog models of digital systems during the design phase by a developed simulation-based fault injection tool called INJECT. With this fault injection tool, it is possible to inject crucial fault models in all abstraction levels (such as swith-level) supported by Verilog HDL. Several fault models for injecting into Verilog models are specified and described. Analyzing the results obtained from the fault injections, using INJECT enables system designers to inform from dependable parameters, such as fault latency, propagation and coverage. As a case study, a 32-bit processor, namely DP32, has been evaluated and effects of faults on some important observation points have been presented. In this study, recovered errors are distinguished from those that affected the system behavior. The errors that lead to wrong results are separated from those that do not affect the correct results.