A 10-bit 100-MS/s 2b/cycle-assisted SAR ADC in 180nm CMOS

Abstract

This paper presents a 10-bit 100-MS/s 2b/cycle-assisted SAR ADC in a 180nm CMOS technology. The proposed 2b/cycle-assisted architecture can effectively speed up ADC operation and improve the ADC linearity. To maintain a small capacitor mismatch, dual-reference C-DACs are proposed to avoid using a tiny unit capacitance. At 100-MS/s, it consumes 6.45 mW from a 1.8-V supply. Measured Nyquist SNDR and SFDR are 52.3 and 71 dB, respectively. Measured ENOB is 8.4 bits, equivalent to a FoM of 191 fJ/conversion-step.