A 65nm CMOS 3.6GHz fractional-N PLL with 5th-order ΔΣ modulation and weighted FIR filtering

Abstract

A 3.6GHz fractional-N PLL utilizing high-order digital modulation and weighted 13-tap finite impulse response (FIR) filtering for low spur and enhanced noise reduction is implemented in 65nm CMOS. The prototype PLL exhibits nearly −100dBc/Hz in-band noise contribution and −126.8dBc/Hz phase noise at a 3MHz offset from a 1.8GHz carrier. With 5th-order single-loop ΔΣ modulation, the fractional spur levels of −65.6dBc and −58.5dBc are achieved within the bandwidth and near the bandwidth, respectively.