On high speed add-compare-select for Viterbi decoders

Abstract

Add-compare-select (ACS) operations form the kernel of Viterbi algorithms. Owing to the ostensibly sequential nature of the ACS algorithm, hardware implementations often used to be slower. We propose a concurrent add-compare scheme that completes addition and comparison almost simultaneously. Power delay models that reflect the algorithmic, circuit and technological limitations of the target realization are developed. With radix 2 and 4 ACSs involving 16 bit operands, the proposed schemes offer a worst case delay reduction of better than 10% for sub 0.2 micron CMOS processes.