Energy optimization techniques on SRAM: A survey

Abstract

The need for low-power design is becoming a major issue in high-performance digital systems such as microprocessors, Digital Signal Processors (DSPs) and other applications. The increasing market of mobile devices and battery powered portable electronic systems is creating demands for chips that consume the smallest possible amount of power. On the one hand, hundreds to millions of transistors can be integrated on the same chip using System on Chip (SoC) design methodologies. On the other hand, the shrinking feature sizes and increasing circuit speed causes higher power consumption, which not only shorten the battery life of handheld devices, but also lead to thermal and reliability problems. Until now various techniques of energy optimization have come forward and effectively contributed to the problem of energy optimization. In this paper, we discuss the various factors for designing the low power SRAM cells by analyzing the power dissipation issues by considering the basic Static Random Access Memory (SRAM) structure and concentrate on supply voltage, parallelism and memory architecture. Regarding the supply voltage, the voltage scaling technique with hybrid parallelism is surveyed and various cache architectures for memory has been addressed to optimize the energy. The energy optimization in memory array could be achieved by an efficient SRAM cell along with sense amplifiers and read write circuitry.