An all-digital Built-In Self-Test for Charge-Pump Phase-Locked Loops

Abstract

Mixed-signal testing is becoming an important issue that affects both the time-to-market and product cost of many SoCs. This paper presents an effective Built-in Self-Test (BIST) method of Charge-Pump Phase-Locked Loops (CP-PLL) which is a mixed-signal circuit widely used in most of SoCs. This BIST will use the existing circuits units as test device in the test mode. It can be easily implemented with several logic gates combined with some delay units and the test output is purely digital. The simulation results show higher fault coverage and lower area overhead than that of previous test methods. Thus it provides an efficient structural test which is suitable for a production test.