A hardware architecture binarizer design for the H.264/ AVC CABAC entropy coding

Abstract

The CABAC (Context Adaptive Binary Arithmetic Coding) in the H.264/AVC standard consists of binarizer, arithmetic encoder, and bit generator. This paper presents hardware architecture design of the binarizer part of the CABAC (Context-Based Adaptive Binary Arithmetic Coding) entropy encoder as defined in the H.264/AVC video compression standard. The proposed architecture avoids the support of all the binarizer method. The proposed architecture avoids the support of all the binarizer method. After implemented in Verilog-HDL and synthesized with Xilinx ISE Design the proposed architecture consumes about 394 slices and can operate at frequencies up to 267 MHz.