Testing of Logic Blocks Using Built-In Self Test Scheme for FPGAs

Abstract

Any FPGA structure has interconnect cells, configurable logic blocks and I/O pads. The physical path between the blocks form interconnects. The logic blocks may have both combinational and sequential circuits to perform logic functions. Here the logic blocks are assumed to have either combinational or sequential circuits which generate a single minterm or maxterm as the output. The FPGA testing is divided into interconnect and logical testing. In interconnect testing fault models are introduced in the wire connections that exists within logic blocks and these faults are propagated to the output thereby detecting the faults at interconnects. In general 2n test vectors are needed to test the single term logic function with n inputs. Here Walsh code is used to optimize the test vectors. The number of test vectors are optimized as log2(M+2), where M is number of wire connections. The test vectors are the columns of M binary numbers and the successive binary numbers are exchanged to obtain the test vectors