Improvement of damping impedance method for Power Hardware in the Loop simulations

Abstract

The aim of this study is to present an improvement of the Damping Impedance Method (DIM) Interface Algorithm for Power Hardware in the Loop (PHIL) simulations. The improvement is based on the calculation of the Hardware Under Test (HUT) impedance, in order to include it as part of the Damping Impedance Method to enhance its accuracy and stability. To verify the results, the improved DIM interface is simulated using MATLAB/Simulink, furthermore, a laboratory implementation of a PHIL simulation is carried out using a variable load. The stability of the interface algorithm is graphically observed using the Nyquist and Bode stability criteria, whereas the precision is validated through simulations that compare the Mean Square Error (MSE), as well as laboratory experiments.