Stack gate technique for minimizing leakage current in multigate MOSFETs

Abstract

FinFETs are considered to be one of the promising devices to extend the CMOS technology beyond the scaling limit of conventional CMOS technology. FinFETs mass manufacturing has been made successfully on bulk and on silicon-on-insulator (SOI) wafers. Additional processes are needed to suppress the leakage current in the case of bulk. In this paper, stack gate technique to suppress the leakage current is proposed with a gate length of 10nm and the performance characteristics are analyzed through ON current, OFF current, Ion/Ioff ratio, DIBL (Drain Induced Barrier Lowering), and SS (subthreshold slope) through 3-D TCAD simulation, metal gates are shown to be feasible. A comparison of both vertically stacked gate and horizontally stacked gates has also been presented.