Viterbi decoder architecture for interleaved convolutional code

Abstract

Sn area efficient high speed Veterbi decoder architecture, which is based on the state-parallel architecture with register exchange path memory structure, for interleaved convolutional code is proposed By replacing each delay (or storage) element in state metrics memory (or path metrics memory) and path memory (or survival memory) with I delays, interleaved Viterbi decoder is obtained. The decoding speed of this decoder architecture is as fast as the operating clock speed. The latency of proposed interleaved Viterbi decoder is "decoding depth (DD) /spl times/ interleaving degree (I)', which is linearly increased with the interleaving degree I.