FPGA-based Learning Acceleration for LSTM Neural Network

Parallel Process. Lett. Pub Date : 2022-10-27 DOI:10.1142/s0129626423500019

G. Dec

引用次数: 1

Abstract

This paper presents and discusses the implementation of a learning accelerator for an LSTM neural network that utilizes an FPGA. The accelerator consists of a backpropagation through time algorithm for an LSTM. The presented net performs a binary classification task and consists of an LSTM and a dense layer. The performance is then compared to both a hard-coded Python implementation and an implementation using Keras library and the GPU. The implementation is executed using the DSP blocks, available via the Vivado Design Suite, which is in compliance with the IEEE754 standard. The results of the simulation show that the FPGA implementation remains accurate and achieves higher speed than the other solutions.

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基于 FPGA 的 LSTM 神经网络学习加速

本文介绍并讨论了利用 FPGA 实现 LSTM 神经网络的学习加速器。该加速器由 LSTM 的时间反向传播算法组成。提出的网络执行二进制分类任务，由一个 LSTM 和一个密集层组成。然后将其性能与硬编码 Python 实现和使用 Keras 库和 GPU 的实现进行比较。该实现是使用符合 IEEE754 标准的 DSP 模块（可通过 Vivado 设计套件获得）执行的。仿真结果表明，与其他解决方案相比，FPGA 实现仍然准确，速度更高。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Parallel Process. Lett.

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