An Integrated Circuit Placement Algorithm Considering Exposure Optimization

Abstract

Objective: Exposure is one of the important steps in semiconductor production. During exposure, semiconductor devices should be kept at a small geometric distance to improve space utilization. How to consider the exposure optimization in the placement process and reduce the process error is a valuable problem. Methods: In this paper, we studied the optimization of wafer exposure pattern, and divided the IC layout optimization problem into two steps. Firstly, based on the idea of greed, orthogonal rectangular devices are packaged into rectangles to improve the local space utilization as much as possible. For rectangle splicing, we have designed a set of prior rules to make the wafer exposure mode tend to be similar in aspect ratio and small in total area. At the same time, we have designed an improved pheromone storage structure to optimize the two-dimensional layout through ant colony algorithm. Results: In the experimental stage, we use the ant colony algorithm to optimize the overall two-dimensional placement combined with prior rules to test. Experiments show that our ant colony algorithm performs better in technical indicators, especially in the aspect ratio control is very strict. In the layout test of 10 rectangular devices and 9 polygonal devices, the area utilization reaches 0.87, takes 9 seconds, and the aspect ratio is 1.02. Conclusions: We tested the algorithm on the multi project wafer placement test data provided by Huada Jiutian, and achieved better results than the baseline ant colony algorithm.