A new lower power Viterbi decoder architecture with glitch reduction

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824034

J. Ryu, S. C. Kim, J.D. Cho, H.W. Park, Y. Chang

引用次数: 3

Abstract

This paper presents a new algorithm for a lower power Add-Compare-Select (ACS) architecture and glitch minimization for the Viterbi decoder which can reduce the complexity of the computation using HSPICE. Our experimental results show an average 7% reduction in power with the same latency at a cost of 3% increase in area compared with the ACS unit introduced by Tsui et al. (1999).

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一种新的低功耗Viterbi解码器架构，减少了故障

本文提出了一种低功耗的Viterbi译码器ACS (add -比较- select, ACS)结构和差错最小化算法，可以降低HSPICE算法的计算复杂度。我们的实验结果表明，与Tsui等人(1999)介绍的ACS单元相比，在相同延迟的情况下，功耗平均降低7%，面积增加3%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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