Hardware implementation of fast high dynamic range processor for real-time 4K UHD video

Abstract

The high dynamic range (HDR) has become very important because of the rapid increase in demand for a variety of applications. However, most of them were implemented by expensive systems due to the high complex computation for processing the real-time 4K UHD video. In the proposed hardware, the non-linear camera response function (CRF) with the area optimization of logarithmic computations has been applied to improve HDR quality. And, for embedding in Field Programmable Gate Array (FPGA), we implement a dedicated hardware using 4006 lookup table (LUT) and 21KB sized internal memory. The proposed architecture enables a real-time HDR processing with pipelining for a UHD video (8 Mega pixels) at 30 frames per second.