A detailed router for hierarchical FPGAs based on simulated evolution

Abstract

This paper presents a new detialed router for the hierarchical field programmable gate arrays (H-FPGAs). The optimal objectives of proposed routing algorithm are improving the time consumption of routing procedure (minimizing the running time of algorithm), and at the same time make great effort to decrease the wire length and critical path delay. Initially, nets are routed sequentially according to their criticalities. Then, to achieve optimization targets, the nets violating routablity constrains are resolved iteratively by a rip-up and rerouting router using the simulated evolution optimization technique, where each net will be evaluated via a rip-up priority function consisting of the timing part and the congestion part, and then compared to a random number to decide if it will be ripped and rerouted. An experimental result under commercial H-FPGA shows that our router can have about 26% improvement on the time-consumption and 0.45% reduction on total wire length when compared with a modified VPR.