A high-level timing model for variability characterization of interconnect circuits

Abstract

At nanometer nodes (e.g., 45nm and beyond), stochastic fluctuations on the implemented features and doping levels during the processing of devices is making the electrical parameters of wires and transistors to become more unpredictable, resulting in process variability. Designers cannot neglect the impact of variability on their designs any more, not only during physical design but also during logic synthesis. They need to account for its impact on the timing of the interconnect to make sure that timing closure is achieved and that the design is manufacturable with an acceptable parametric yield. This paper presents a high-level timing model and tool for analyzing typical interconnect circuits accounting for modeling of process variability in the drivers present in the net which is fast enough to be used for Monte-Carlo variability characterization. The approach provides speed-ups between three to four orders of magnitude with very high accuracy when compared to plain SPICE simulation using a 32nn predictive technology model BSIM4 model card