Trigger and readout electronics for the phase-I upgrade of the ATLAS forward muon spectrometer

Abstract

The upgrades of the LHC accelerator and the experiments in 2019/20 and 2023/24 will increase the instantaneous and integrated luminosity, but also will drastically increase the data and trigger rates. To cope with the huge data flow while maintaining high muon detection efficiency and reducing fake muons found at Level-1, the present ATLAS small wheel muon detector will be replaced with a New Small Wheel (NSW) detector for high luminosity LHC runs. The NSW will feature two new detector technologies: resistive micromegas (MM) and small strip Thin Gap Chambers (sTGC) conforming a system of ∼2.4 million readout channels. Both detector technologies will provide trigger and tracking primitives. A common readout path and a separate trigger path are developed for each detector technology. The electronics design of such a system will be implemented in about 8000 front-end boards, including the design of a number of custom radiation tolerant Application Specific Integrated Circuits (ASICs), capable of driving trigger and tracking primitives to the backend trigger processor and readout system. The large number of readout channels, the short period of time available to prepare and transmit trigger data, the high-speed output data rate, the harsh radiation environment, and the low power consumption, all impose great challenges to the system design. The overall design, development and performance of various prototypes and integration efforts will be presented.