A Configurable Linear PA Ramp Controller for DSRC Applications in 130 nm CMOS Technology

Abstract

In this paper, a configurable linear ramp controller (CLRC) for power amplifier (PA) is proposed. It changes PA core size linearly for amplitude shift keying (ASK) modulation and improves PA power controllability. The configurable ramping reduces harmonics and spurious in PA output power spectrum and improves PA performance. The proposed controller uses standard cells for the unit delay and it is fully synthesizable. The ramping step size is configurable between 0.2 ns to 0.7 ns. It needs 51.73 K gate counts for its implementation. The design consumes 863 μW power and draws 719 μA current from 1.2 V supply. The proposed controller is integrated into DSRC transceiver and is implemented in 130 nm CMOS technology. It occupies 314 μm × 314 μm of chip area.