Xu Jin, Huapeng Xiao, Dong Wu, Ning Deng, Huaqiang Wu, Kanyu Cao, H. Qian
{"title":"A novel speed-up coding method in quadruple-level-cell 3D NAND flash memory","authors":"Xu Jin, Huapeng Xiao, Dong Wu, Ning Deng, Huaqiang Wu, Kanyu Cao, H. Qian","doi":"10.1109/ISNE.2016.7543285","DOIUrl":null,"url":null,"abstract":"As more and more demand on high density storage, 3D NAND Flash memories have developed into multi-level cell and triple-level cell. With the charge-trapping technology adopted in 3D NAND Flash, it is possible to achieve quadruple-level-cell (QLC) which brings higher density capability. Meanwhile, the program coding method makes significant impact on the efficiency of the lockout operation in the program verification. A novel speed-up coding method is presented in this paper, which reduces nearly 30% time delay and 40% power consumption during the verify lockout operation in the QLC memory.","PeriodicalId":127324,"journal":{"name":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","volume":"63 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 5th International Symposium on Next-Generation Electronics (ISNE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISNE.2016.7543285","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
As more and more demand on high density storage, 3D NAND Flash memories have developed into multi-level cell and triple-level cell. With the charge-trapping technology adopted in 3D NAND Flash, it is possible to achieve quadruple-level-cell (QLC) which brings higher density capability. Meanwhile, the program coding method makes significant impact on the efficiency of the lockout operation in the program verification. A novel speed-up coding method is presented in this paper, which reduces nearly 30% time delay and 40% power consumption during the verify lockout operation in the QLC memory.