Compact ultra low power class AB buffer amplifier

Ali Far
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引用次数: 2

Abstract

Targeting the energy harvesting applications that require multiple channels of matched buffer amplifiers on a chip, a small rail-to-rail input-output, ultra low current, and low supply voltage (VDD) buffer amplifier is presented. The contributions of this work are as follows: First, an output buffer driver utilizes a loser-take-all circuit (LTA) and a current mirror amplifier (CMA) circuit to regulate the current in either of the inactive sink or source output driver transistors (FET). In conjunction with the LTA and CMA, a complementary noninverting current mirror (CNICM), monitors and rectifies the sink-source output signals before they are fed to the LTA circuit. Hence, the amplifier's current consumption, attributed to monitoring external loads, is substantially curbed. More importantly, because all the elements of the buffer driver (LTA, CMA, and CNICM) operate mainly in current mode, the output buffer driver is structurally fast and can operate with low VDD of about VGS+2VDS. Second, a floating current source (FCS) function is emulated that can also operate with low VDD and is fast in lieu of utilizing auxiliary common gate amplifiers (CGA). The FCS contains two complementary cascoded FET current sources where the middle cascoded FET's VGSs are held constant and their drain currents are criss-crossed and fed to each other's source terminals, while CGAs regulate the VGSs of the lower FETs, whose currents are substantially equalized and mirrored into the Amplifier's bias network. Montecarlo (MC) and worst case (WC) simulations indicate the following specifications are achievable: VDD minimum ∼ 0.8v; IDD ∼ 200nA; input voltage range rail to rail; output voltage range ∼ 10mV from the rails; open loop gain (AV) ∼ 115dB with unity gain bandwidth (fU) ∼ 600KHz and phase margin (PM) ∼ 30 degrees; power supply rejection ratio (PSRR) ∼ − 88dB; common mode rejection ratio (CMRR) ∼ − 120dB; slew rate (SR) ∼ 2V/ 5uS; settling time (tS) ∼ 10uS; output resistor (RL) capability ∼10K Ohms; and die size rough estimate is 100 um per side.
紧凑型超低功耗AB级缓冲放大器
针对能量采集应用中需要在一个芯片上匹配多个通道的缓冲放大器,提出了一种小型轨对轨输入输出、超低电流和低电源电压(VDD)的缓冲放大器。这项工作的贡献如下:首先,输出缓冲驱动器利用一个失败者通吃电路(LTA)和一个电流镜像放大器(CMA)电路来调节非活动吸收或源输出驱动晶体管(FET)中的电流。与LTA和CMA一起,一个互补的非反相电流镜(CNICM)在将汇源输出信号馈送到LTA电路之前对其进行监测和整流。因此,放大器的电流消耗,归因于监测外部负载,是大大遏制。更重要的是,由于缓冲驱动器的所有元件(LTA, CMA和CNICM)主要工作在电流模式,因此输出缓冲驱动器结构快速,可以在VGS+2VDS左右的低VDD下工作。其次,模拟了浮动电流源(FCS)功能,该功能也可以在低VDD下工作,并且可以快速替代辅助共门放大器(CGA)。FCS包含两个互补的级联FET电流源,其中中间级联FET的vgs保持恒定,它们的漏极电流交叉并馈电到彼此的源端,而CGAs调节较低FET的vgs,其电流基本均衡并镜像到放大器的偏置网络中。蒙特卡罗(MC)和最坏情况(WC)模拟表明以下规格是可以实现的:VDD最小~ 0.8v;IDD ~ 200nA;输入电压范围轨到轨;输出电压范围从轨~ 10mV;开环增益(AV) ~ 115dB,单位增益带宽(fU) ~ 600KHz,相位裕度(PM) ~ 30度;电源抑制比(PSRR) ~−88dB;共模抑制比(CMRR) ~−120dB;压转率(SR) ~ 2V/ 5uS;沉降时间(tS) ~ 10uS;输出电阻(RL)能力~ 10K欧姆;模具尺寸粗略估计是每边100微米。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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