Interactive learning toolbox for logic synthesis with VHDL

Abstract

With the advance in Computer-Aided Design (CAD) technology, digital design in VLSI has moved from the bottom-up design approach to top-down design methodology with the aid of advanced Electronic Design Automation (EDA) tools. The most common design platform is one in which the tools make use of VHDL as the design medium. It has become the standard approach for designing digital circuit/systems. However, mastering VHDL for design is not as simple as it seems, in that it is simply high level programming to mimic the design hardware, even for experienced designer. An interactive learning tool with the capability of conducting experiments concurrently is proposed to enhance the teaching quality and provide ample training for students in learning VHDL.