High performance low voltage low power voltage mode analog multiplier circuit

T. Ettaghzouti, N. Hassen, K. Besbes
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引用次数: 5

Abstract

This paper presents a low voltage low power analogue voltage mode four quadrant multiplier circuit using only two second generation current conveyor circuits (CCII) and two NMOS transistors operating in ohmic region. This circuit is characterized by ± 0.25 V dynamic ranges with a low total harmonic distortion (THD) around to 0.021 %, wide bandwidth (2.67 GHz) and low power consumption of about 0.43 mW. Tspice simulations using 0.18 µm CMOS TSMC parameters are performed to confirm the workability of CCII circuit and voltage mode multiplier structure.
高性能低电压低功率电压模模拟倍增电路
本文提出了一种低压低功耗模拟电压模式四象限乘法器电路,该电路仅使用两个工作在欧姆区的NMOS晶体管和两个第二代电流传输电路。该电路的动态范围为±0.25 V,总谐波失真(THD)约为0.021%,带宽(2.67 GHz)宽,功耗约为0.43 mW。采用0.18µm CMOS TSMC参数进行了Tspice仿真,验证了CCII电路和电压模倍增器结构的可操作性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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