Spyder: a reconfigurable VLIW processor using FPGAs

[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines Pub Date : 1993-04-05 DOI:10.1109/FPGA.1993.279483

C. Iseli, E. Sanchez

引用次数: 83

Abstract

A processor with multiple reconfigurable execution units has been designed and implemented. The reconfigurable execution units are implemented using reprogrammable field programmable gate array (FPGA) chips. The architecture and implementation of this processor are described in detail. An example shows that this reconfigurable processor is able to compute the new state of 100'000'000 cells of Conway's game of life per second with a clock speed of 6.25 MHz.<>

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Spyder:一个使用fpga的可重构VLIW处理器

设计并实现了具有多个可重构执行单元的处理器。可重新配置的执行单元使用可重新编程的现场可编程门阵列(FPGA)芯片实现。详细描述了该处理器的体系结构和实现。实例表明，该可重构处理器能够以6.25 MHz.>的时钟速度每秒计算出康威生命游戏的100万亿个细胞的新状态

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

[1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines

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