A scalable low-complexity digit-serial VLSI architecture for RSA cryptosystem

Abstract

The Booth-encoded Montgomery modular multiplication algorithm is proposed to reduce the iteration number to about n/2 in each Montgomery operation. In addition, we apply the folding and unfolding technique to shorten the critical path. Finally, we propose the 2 bit-digit-serial pipelined architecture to process RSA en/decryption in a more efficient way. By applying the proposed algorithm in RSA design, the hardware complexity can be reduced by 15% compared with most RSA VLSI designs using the Montgomery modular multiplication algorithm.