Keonhee Cho, Heekyung Choi, I. Jung, J. Oh, Tae Woo Oh, Kiryong Kim, Gi-Kryang Kim, T. Choi, Changsoo Sim, T. Song, Seong-ook Jung
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引用次数: 4
Abstract
This paper presents SRAM write- and performance-assist cells that have bit-cell compatible layouts and thus can be inserted into an bit-cell array without the white space. The proposed cells can effectively resolve the degradation in write-ability and performance caused by the interconnect resistance increased with technology scaling.
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