An Area-Efficient Current Quantization Circuit Inspired by Digital Low-Dropout Regulators

Abstract

This paper presents a novel current quantization circuit which applies the operating principles of digital low dropout regulator (DLDO). Compared with the traditional current quantization designs, the proposed circuit can save chip area as much as 66% under the same quantization range and resolution. Implemented in 130 nm CMOS process, the prototype circuit can sense current under 1 mA with 8-bit resolution, and only occupies 0.02mm2 chip area. This design can also be expanded to wider range and higher resolution.