A 2.4GHz 2Mb/s digital PLL-based transmitter for 802.15.4 in 130nm CMOS

M. Ghahramani, M. Ferriss, M. Flynn
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引用次数: 5

Abstract

A fully integrated 2.4GHz transmitter for 802.15.4 based on a digital ΣΔ fractional-N PLL is presented. A self-calibrated two-point modulation scheme enables modulation rates much larger than the loop bandwidth. An oversampled 1-bit quantizer is used as a phase detector, reducing spurs and nonlinearity associated with some TDC-based digital PLLs. The prototype achieves an MSK modulation rate of 2Mb/s, delivers −2dBm of output power, and is free of in-band fractional spurs. The transmitter, implemented in 130nm CMOS, consumes 17mW from a 1.2V supply and occupies an active area of 0.6mm2.
一个2.4GHz 2Mb/s的数字锁相环发射机802.15.4在130nm CMOS
提出了一种基于数字ΣΔ分数n锁相环的802.15.4全集成2.4GHz发射机。自校准两点调制方案使调制速率远远大于环路带宽。过采样的1位量化器用作鉴相器,减少了与一些基于tdc的数字锁相环相关的杂散和非线性。该原型实现了2Mb/s的MSK调制速率,输出功率为- 2dBm,并且没有带内分数杂散。该发射器采用130nm CMOS, 1.2V电源消耗17mW,占用0.6mm2的有效面积。
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