Area-Aware Design of Static CMOS Complex Gates

Abstract

Concerning the digital VLSI design, recent papers have pointed several optimizations in circuits composed of Static CMOS Complex Gates when compared to the widely applied standard cell library project based. In this scenario, one of the major steps in the complex gate design is the transistor network generation, responsible for delivering the specialized logic arrangement that implements the desired Boolean function. The methodologies that perform this task typically aims to obtain solutions with a fewer number of transistors, since it potentially produces optimized circuits. In this paper we analyze the impact in the layout area of non-planar circuits obtained through the state of the art transistor network generation methodology, proposing a new approach for the logic design of these specific cells. The results have shown that our method, even producing versions with a larger number of transistors, can achieve geometrical optimizations when compared to the complex gate cells generated under the state of the art methodology.