Extending on-die wiring hierarchy with wafer level packaging concepts

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) Pub Date : 2004-06-07 DOI:10.1109/IITC.2004.1345705

J. Balachandran, S. Brebels, G. Carchon, T. Webers, W. De Raedt, B. Nauwelaers, E. Beyne

引用次数: 6

Abstract

Wafer level package (WLP) redistribution layer interconnects can be effectively used for countering on-die global wiring challenges. To demonstrate this, we fabricated WLP test chips with two configurations namely IMPS and microstrip transmission lines in WLP layers. Experimental results indicate superior electrical performance. Near speed of light propagation is observed with insignificant signal distortion. We compare the WLP layers interconnect performance with a representative 70nm node upsized global interconnect. Details on the WLP technology are also provided.

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用晶圆级封装概念扩展片内布线层级

晶圆级封装(WLP)再分配层互连可以有效地用于应对芯片上的全局布线挑战。为了证明这一点，我们在WLP层中制作了两种配置的WLP测试芯片，即IMPS和微带传输线。实验结果表明，该材料具有优良的电气性能。光的传播速度接近，信号失真不明显。我们将WLP层互连性能与具有代表性的70nm节点放大全局互连进行了比较。还提供了WLP技术的详细信息。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)

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