Y. Kohno, T. Kunii, T. Oku, R. Hattori, J. Udomoto, M. Komaru, K. Yajima, A. Inoue, K. Itoh, H. Takano, O. Ishihara, S. Mitsui
{"title":"K-band high gain and high reliability GaAs power FET with sub-half micron WSi/Au T-shaped gate","authors":"Y. Kohno, T. Kunii, T. Oku, R. Hattori, J. Udomoto, M. Komaru, K. Yajima, A. Inoue, K. Itoh, H. Takano, O. Ishihara, S. Mitsui","doi":"10.1109/GAAS.1994.636950","DOIUrl":null,"url":null,"abstract":"We have developed a K-band GaAs power MESFET with 0.35 /spl mu/m WSi/Au T-shaped gate structure. This structure has been realized by forming a SiO/sub 2/ sidewall at both sides of recess, so the gate length is easily reduced to sub-half micron. A gate-to-drain breakdown voltage (Vgdo) of over 15 V, which depends strongly on the distance between gate edge and recess edge, is achieved when the sidewall width is adjusted to be more than 0.25 /spl mu/m. The 900 /spl mu/m gate-width FET has delivered an output power at 1 dB gain-compression point of 27.2 dBm with a linear gain of 9.5 dB at 18 GHz. An excellent mean time to failure (MTTF) of over 3E7 hours at Tch=125/spl deg/C has been obtained for the WSi/Au gate FET.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE GaAs IC Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1994.636950","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
We have developed a K-band GaAs power MESFET with 0.35 /spl mu/m WSi/Au T-shaped gate structure. This structure has been realized by forming a SiO/sub 2/ sidewall at both sides of recess, so the gate length is easily reduced to sub-half micron. A gate-to-drain breakdown voltage (Vgdo) of over 15 V, which depends strongly on the distance between gate edge and recess edge, is achieved when the sidewall width is adjusted to be more than 0.25 /spl mu/m. The 900 /spl mu/m gate-width FET has delivered an output power at 1 dB gain-compression point of 27.2 dBm with a linear gain of 9.5 dB at 18 GHz. An excellent mean time to failure (MTTF) of over 3E7 hours at Tch=125/spl deg/C has been obtained for the WSi/Au gate FET.